interface ic2_if(input bit clk);
logic   rst;
logic   sda;
logic   scl;

logic   [7:0] myReg0;

clocking drvclk @(posedge clk)
  output sda;
  output scl;
  input myReg0;
endclocking:drvclk


clocking monclk @(posedge clk)
  input sda;
  input scl;
  input myReg0;
endclocking:monclk

endinterface //ic2_if
